A novel buffering fault‐tolerance approach for network on chip (NoC)

Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC network-based subsystem on an integrated circuit, most typically modules system (SoC). Designing reliable against failures that can prevent failure using some measures or preventing error while happens and proper performance became significant concern. For design failures, first, the should be analysed to discover critical points. Hence, this research, tried first investigate scale of fault tolerance effect mechanism router network by injecting simulated errors, then these errors are prevented. As major novelty, authors implemented synchronised calculated buffering buffer. Specifically, new method for improving proposed, which uses existing resources efficiently. So, does not impose any overhead hardware improves scale. The also evaluate from different perspectives show its superior performance.